Layout versus schematic (LVS) verification prior to tape-out is a critical step to avoid costly errors and program delays. Historically this important process has often involved a separate tool or manual workarounds for compound semiconductor MMICs.
This case study highlights how Altum RF, WIN Semiconductors, and Keysight collaborated to enhance Desktop LVS capabilities within Keysight Advanced Design System (ADS) for WIN Semiconductor’s Process Design Kits (PDKs), enabling designers to complete a thorough LVS check within a familiar, integrated EDA environment. The improved capabilities support Altum RF’s use of customized layout cells that enable performance improvements for millimeter-wave applications.
By simplifying verification and reducing manual review, engineers can spend less time checking layouts and more time advancing designs toward tape-out with confidence.
Explore the full case study on the Keysight website:
Desktop LVS for MMIC Designs Using WIN Semiconductors PDK | Keysight
